This invention relates to an improved pulse counter-type FM detector circuit.
FIG. 1 is a block diagram of a conventional pulse counter-type FM detector circuit. The FM signals applied to input terminal 1 are shaped into pulse signals by a limiter circuit 2, changed to trigger pulses by a trigger pulse generating circuit 3, and are converted into pulse signals having a fixed width by a monostable circuit 7 which is comprised of a gate circuit 4, a differentiating circuit 5, and an inverter circuit 6. The audio signals detected at the output terminal 9 are obtained through the integrator 8.
As previously described in Japanese Utility Model Application No. Sho-52(1977)-141079 and as illustrated in FIG. 2 of the present application, a circuit superior to the pulse counter-type FM detector circuit of FIG. 1 can result in reduced output of high frequency radiation and increased demodulated output by using a differential amplifier circuit that functions as a current switch for inverter circuit 6 of monostable circuit 7. Also, the inverted output applied to integrator 8 may be obtained from the side of the differential inverter circuit that is not used for feedback, this having been described in Japanese Patent Application No. Sho-51(1976)-69606 and also illustrated in FIG. 2.
When the frequency of the FM signals to be detected is relatively low and sufficiently removed from the upper limit frequency of the demodulated output signals, a low pass filter using coils and capacitors--for example, a Tchebychef type filter or the like, is used as integrator 8, this also being shown in FIG. 2. As will be described in more detail hereinafter, the low pass filter has to be of a type that significantly reduces the amplitude of the output pulse signal at the output terminal of the above-mentioned differential inverter circuit in order to reduce negative feedback in the high frequency range of the differential inverter circuit and thus stabilize the pulse width of the output pulse signal. This problem is also discussed in Japanese Patent Application No. Sho-53(1978)-114281 and aforementioned U.S. application Ser. No. 74,680. When the amplitude of the output pulse signal of the inverter circuit is too large, a lower dynamic range results due to transistor saturation in the inverter circuit.
FIG. 2 illustrates in more detail typical portions of the pulse counter-type FM detector circuit of FIG. 1 presently under consideration. The trigger pulses from the trigger pulse generating circuit 3 (not shown in FIG. 2) are applied to input terminal 1'. NAND gate circuit 4 is connected to differential inverter circuit 6 through the differentiating circuit 5. In differential inverter circuit 6, the emitters of transistors Q.sub.1 and Q.sub.2 are connected in common and then connected to a negative power supply (-B) through a constant current source I.sub.s. The collector of transistor Q.sub.1 is connected to a positive power supply (+B.sub.1) through a resistor R.sub.2 and the collector of transistor Q.sub.2 is connected to a positive power supply (+B.sub.2) through a resistor R.sub.3. The collector of transistor Q.sub.1 is also connected to one input terminal of gate circuit 4 while the collector of transistor Q.sub.2 is connected to capacitor C.sub.5 and resistor R.sub.4 through a Tchebychef type low pass filter 10 (simply noted as LPF hereafter) which is comprised of coils L.sub.1 and L.sub.2, and capacitors C.sub.2, C.sub.3, and C.sub.4. The base of transistor Q.sub.1 is connected to the connection point of the DC power supplies E.sub.1 and E.sub.2 through the parallel circuit of resistor R.sub.1 and diode D while the base of transistor Q.sub.2 is connected to the negative power supply (-B) through the power supplies E.sub.1 and E.sub.2.
The operation of the conventional pulse counter-type FM detector circuit of FIG. 2 will now be described. When the FM signal which has been converted to a negative trigger pulse is applied to the input terminal 1', a positive pulse signal is outputted from NAND gate circuit 4, this positive pulse signal being converted to a differential pulse by differentiating circuit 5. Transistor Q.sub.2 is normally in an ON-state while transistor Q.sub.1 is normally in an OFF-state. Assume a positive differential pulse is applied to the base of transistor Q.sub.1. During the rise time of this pulse, transistor Q.sub.1 is placed in the ON-state and transistor Q.sub.2 in the OFF-state. The base potential of transistor Q.sub.1 will then drop in accordance with the time constant C.sub.1 R.sub.1 of the differentiating circuit 5 so that transistor Q.sub.1 will change back to the OFF-state and transistor Q.sub.2 to the ON-state at or below the threshold level thereof. A positive signal with a time width of C.sub.1 R.sub.1 seconds is thus obtained from the output of transistor Q.sub.2 , and a detected audio signal is obtained at output terminal 9 through integrator 8.
The input capacity of LPF 10 must be rather large in order to reduce the negative feedback sufficiently in the treble range of the differential inverter circuit. Therefore, the insertion loss of the LPF is normally around 6 dB, which is relatively large.
The detector output level at output terminal 9 is proportional to the constant current source I.sub.s and to load resistor R.sub.3 where the output current of the constant current source and the resistance of the load resistor are determined by the dynamic range of the differential amplifier used. In the conventional pulse counter-type FM detector circuit of FIG. 2, the terminal resistor R.sub.4 of the LPF is connected to the output terminal of LPF 10 via capacitor C.sub.5 and not DC-coupled to the output terminal of the differential inverter circuit 6 through coils L.sub.1 and L.sub.2 of LPF 10. Consequently, the current capacity of the constant current source I.sub.s cannot be increased and the insertion loss of LPF 10 cannot be compensated. Since this insertion loss of LPF 10 reduces the output signal level of the amplifier (not shown) in the following stage connected to terminal 9, it interferes with improvement of the S/N.